-- ir
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ir is
port (
LdIR : in STD_LOGIC_VECTOR(7 downto 0);
Clk : in STD_LOGIC_VECTOR(7 downto 0);
DataIn : in STD_LOGIC_VECTOR(15 downto 0);
DataOut : out STD_LOGIC_VECTOR(15 downto 0)
);
end ir;

architecture behavior of ir is
signal IntData : STD_LOGIC_VECTOR(15 downto 0);
begin
process (LdIR, Clk, DataIn) begin
if (Clk'event and Clk = '1') then
if LdIR = '1' then IntData <= DataIn;
else DataOut <= (others => '0');
end if;
end if;
end process;

DataOut <= IntData;
end behavior;

:cool: allo geng.....apa khabar? mane budak UTM yg lain......takan ni aje  ........wei sapa budak Dip. Kej. Kimia batch 94-97 contact ler aku.......takpun join group ni......DKK_1994-97@yahoogroups.com

lyn..tulla..skang dah jd name org..ktf...takde agi dah name pokok kayu ni..mcm cengal..meranti..tp arked2 yg baru dibina tu jd name arked cengal ngan arked meranti...
dtgla jenguk...takkan dah x kenal lecturer kot...

lyn76 dan belut_nakal : keje kat mane skang ni...